A DICE Flip-Flop Design by Resetting Redundancy Hardening for Single Event Upset Tolerance

The standard cell library forms the foundation of chip design. Conducting rational and efficient radiation-hardening design and performance verification for the library is essential to ensure the safe on-orbit operation of aerospace components. This paper investigates the resettable dual interlocked storage cell (DICE) flip-flop (DICE-FF) from a radiation-hardened cell library and proposes a flip-flop (DICE-REFF) with reset-redundant control circuitry to improve its radiation tolerance. The study examines the effects of Single Event Upset (SEU) both before and after the redundancy hardening of the reset control, identifying sensitive layout regions and critical circuit nodes. Simulations show that the redundancy-hardened DICE-REFF demonstrates strong SEU tolerance, with a Linear Energy Transfer (LET) threshold of 37 MeV/mg/cm2. Additionally, the circuit area increased by only 5% compared to the non-hardened design, with no loss in performance. Additionally, a test chip was designed, and the SEU resistance of the flip-flop was validated through both fault injection and irradiation experiment. The study also explores the impact of different implementation strategies on fault rates.