Warpage Control Strategy of Embedded Die Packaging on SESUB Technology

As the global demand for embedded components in substrates continues to grow, Semiconductor Embedded in Substrate (SESUB) technology has been proposed to meet functions of smaller form factors, higher performance, low power consumption and better heat dissipation. In this work, strip-level warpage was firstly measured by 3D-DIC (Digital Image Correlation) equipment to monitor warpage during thermal profile. A finite element method (FEM) was constructed and experimentally benchmarked for warpage validation. Taguchi design response shows that substrate resin layer with low CTE property and thinner die thickness as the key factors influencing warpage. Finally, combining all positive factors indicates that optimized design can enhance approximately 49% warpage improvement.