A 32 kb 55 nm Radiation-Hardened SRAM Chip With SEU ≤1.1 E-11 Upsets/Bit-Day, SEL >107.1 MeV ⋅ cm²/mg, and TID >100 Krad(Si) for Space Applications

In this paper, a 32kb radiation-hardened (RH) static random access memory (SRAM) chip, named BH55RHSRAM32K, is proposed and fabricated for space applications. The chip is hardened from the view of the circuit level, layout level, and system level and is fabricated using a 55 nm CMOS process design kit with an RH cell library. At the circuit level, the proposed RH-14T SRAM cell and radiation-hardened pre-charged sense amplifier (RH-PCSA) cell adopt a polarity hardening method, making them fully tolerant of single event upset (SEU). At the layout level, the sensitive nodes in the proposed RH-14T SRAM cell and RH-PCSA cell layouts are isolated. Furthermore, the proposed RH-14T SRAM array adopts a bit-interleaved design, effectively reducing single event double upsets (SEDU). At the system level, an error correction coding (ECC) circuit is implemented to enhance SEU tolerance. Experimental results show that the proposed 32kb RH-SRAM chip can not only obtains superior radiation tolerance, i.e., the SEU $ \leq 1.1$ E-11 upsets/bit-day, the SEL >107.1 MeV $\cdot $ cm ${}^{\textbf {2}}$ /mg, and the TID >100 Krad(Si), but also a faster access speed of <10 ns and a lower write power consumption of 14.664 mW in comparison with the related products.