A Review of Performance Variability in MOSFETs Within VLSI Technology: Sources, Mechanisms, and Mitigation Strategies

As the device dimensions continue to shrink, numerous challenges emerge, significantly impacting the design and fabrication of modern silicon-based integrated circuits (ICs). This work presents a comprehensive analysis of performance variations in metal-oxide semiconductor (MOS) devices of ICs. First, the primary sources of performance variations are explored, including process variations, material properties, device geometry, operating conditions et al. A detailed investigation into random dopant fluctuation, line edge roughness/line width roughness, and work function variation is conducted. Furthermore, the mechanisms causing these variations and their impacts on device parameters such as threshold voltage, mobility, and leakage current are discussed. More importantly, advanced modeling techniques and mitigation strategies are proposed, including optimized doping distributions, improved annealing techniques, the adoption of new device architectures, circuit-level design techniques et al. In addition, this review also highlights the importance of developing accurate models for predicting device performance variations and the ongoing research efforts to address the challenges posed by device scaling. By providing a comprehensive understanding of the sources, mechanisms, and mitigation techniques of performance variations in MOS devices, it aims to provide guideline for future research and development in silicon-based IC technology.