Quantifying Trade-Offs in Power, Performance, Area, and Total Carbon Footprint of Future Three-Dimensional Integrated Computing Systems

To address computing's carbon footprint challenge, designers of computing systems are beginning to consider carbon footprint as a first-class figure of merit, alongside conventional metrics such as power, performance, and area. To account for total carbon $(\text{tC})$ footprint of a computing system, carbon footprint models must consider both embodied carbon $(\mathrm{C}_{\text{embodied}})$ due to emissions during manufacturing, and operational carbon $(\mathbf{C}_{\text{operational}})$ from day-to-day use. Models for $(\mathbf{C}_{\text{operational}})$ are relatively mature due to the direct relationship between $(\mathbf{C}_{\text{operational}})$ and energy consumed while computing. In contrast, models for $\mathrm{C}_{\text{embodied}}$ primarily focus on today's silicon-based technologies, not capturing the wide range of beyond-Si technologies that are actively being developed for future computing systems, including emerging nanomaterials, emerging memory devices, and various three-dimensional (3D) integration techniques. $\mathbf{C}_{\text {embodied }}$ models for emerging technologies are essential for accurately predicting which technology directions to pursue without exacerbating computing's carbon footprint. In this paper, we (1) develop $\mathbf{C}_{\text {embodied }}$ models for $\mathbf{3D}$-integrated computing systems that leverage emerging nanotechnologies. We analyze an example fabrication process that is highly promising for energy-efficient computing: $3\mathbf{D}$ integration of carbon nanotube field-effect transistors (CNFETs) and indium gallium zinc oxide (IGZO) FETs fabricated directly on top of Si CMOS at a 7 nm technology node. We show that $\mathbf{C}_{\text{embodied}}$ of this process is, on average (considering various energy grids), $1.31\times$ higher per wafer vs. a baseline 7 nm node Si CMOS process. (2) As a case study, we quantify tradeoffs in power, performance, area, and tC footprint for an embedded system comprising an ARM Cortex-M0 processor and embedded DRAM, implemented in each of the above processes. For a representative lifetime of the system (running applications from the Embench suite for 2 hours per day over 24 months, with a clock frequency of 500 MHz), we show that the 3D IGZO/CNFET/Si implementation is 1.02 × more carbon-efficient per good die (considering yield) vs. the baseline Si implementation, quantified by the product of tC and application execution time $(tCDP$, an effective metric of carbon efficiency). (3) Finally, we show techniques to quantify carbon efficiency benefits of future computing systems, even when there is uncertainty in carbon footprint models. Specifically, we show how to robustly compare $\text{tCDP}$ for multiple computing systems, given underlying uncertainty in $\mathbf{C}_{\text{embodied}}$, computing system lifetime, carbon intensity (in equivalent grams of CO2 emissions per unit energy consumption), and yield.