Design of a Low-Noise Amplifier for Ultra Low Power Wake-Up Receiver at 433 MHz

The study outlines the development of a low-noise amplifier (LNA) specifically engineered for a 433 MHz wakeup receiver that employs duty cycling. Using a bipolar junction transistor (BJT) architecture, the design prioritizes optimal biasing conditions to strike a crucial balance between three key parameters: power efficiency, signal amplification, and noise performance. This careful optimization aims to maximize the receiver's ability to detect weak signals while keeping power consumption to a minimum. Remarkably, the LNA achieves these results while consuming only 4.8 mA from a 3 V power supply, demonstrating its exceptional energy efficiency for low-power applications. The transistor was stabilized using the collector feedback biasing technique and matched with High-Q RF lumped components. The overall LNA design achieves a 33.03 dB gain for the dual-stage circuit with an input matching parameter $\left(S_{11}\right)$ of ‒10.08 dB and an output matching $\left(S_{22}\right)$ of ‒7.31 dB. Additionally, the noise figure was maintained at an impressively low 1.31 dB, ensuring minimal signal degradation and further enhancing the receiver's sensitivity. Furthermore, the design can be tuned by leveraging off-the-shelf components to accommodate various application-specific requirements in wake-up-based systems. Real measurement results demonstrate robust performance at 433 MHz, validating its suitability for low-power, high-sensitivity applications