A 50-MHz Pulse-Width Modulator Embodying Low-Loss Quasi-Dynamic Comparators for Very High-Frequency DC–DC Converters

In the next-generation Internet of Things (NG-IoT) applications with sub-50-mA loads, the state-of-the-art very high switching frequencies (VHFs, e.g., 50 MHz) dc–dc converters are typically power-inefficient at light loads, e.g., 60%. This is largely due to the high power losses of high-speed static comparators employed in the pulse-width modulator of the VHF converter, e.g., ~40% of the overall power losses. Dynamic comparators may mitigate the high loss, but they are impractical to pulse-width-modulation-based converters due to the high-speed clock generator requirement. To mitigate the power losses, we present a pulse-width-modulator converter embodying a proposed quasi-dynamic (QD) comparator (and its hysteretic variant). The innovation is the first-ever comparator that features a clock-free regenerative latch (CFRL), thereby enabling the comparator to simultaneously feature the high-speed and low-loss advantages of dynamic comparators, yet clockless operation of static comparators. Our 50-MHz pulse-modulator converter, realized in 65-nm CMOS and embodying the proposed QD comparators, features a high ~82% power efficiency at 10 mA (20% of max load)—$\ge$20% higher power efficiency than the state-of-the-art VHF converters. The proposed QD comparator therein dissipates ~145-μW power and features 2.9-ns propagation delay—$\ge$40% lesser power-delay product than the state-of-the-art static comparators. The proposed QD comparator can be advantageously applied to replace static comparators in a myriad of applications, potentially improving their power efficiency without compromising high-speed operation.