A High-Performance Architectural Design for FIR Filtering in Fixed and Reconfigurable Applications

The FIR filter architecture is proposed that achieves high-speed operation focused on both fixed and programmable applications. Instead, we take a transpose form configuration of a block FIR filter in an area-delay efficient way, which is effective for medium-to-large orders of the filters we introduce a generalized block formulation for transpose FIR filters, providing a unified approach for implementation. Moreover, we also present a low-complexity architecture based on the Multiple Constant Multiplication (MCM) strategy for fixed FIR filters, which helps in inordinate reduction in associated complexity and resources. The proposed architecture shows significant savings in terms of the Area-Delay Product (ADP), when compared to the traditional direct-form FIR filter architectures when they are implemented using digital blocks, which is especially true for medium and large sizes. The direct-form implementation is more efficient for low filter lengths, but as they increase, it becomes impractical, where the proposed architecture applies. This renders the design highly beneficial for reconfigurable and resource-efficient FIR filter applications. To verify the functionality of the proposed architecture, the design is coded in Verilog HDL, modeled in ModelSim and synthesized in Xilinx tools. Extensive experimental results validate that the proposed architecture save a huge amount with respect to resource usage as well as delay, thus are very beneficial for future digital signal processing applications. Therefore, the proposed method offers a flexible and efficient design of fixed and reconfigurable FIR filters that meets the increasing demand for high-performance and low-complexity digital filter structures.