A Novel Low-Power Ternary D-Latch based on GNRFET-RRAM

This paper presents a low-power and energy-efficient ternary D-latch design utilizing Graphene Nanoribbon Transistors (GNRFETs) and Resistive Random-Access Memory (RRAM). Exploiting inherent multi-level capabilities of GNRFETs and the non-volatility of RRAM, we achieve a significant reduction in power consumption and improved energy efficiency compared to traditional designs. Furthermore, a comparative analysis against a CNTFET-RRAM D-latch is conducted and demonstrating substantial improvements in terms of propagation delay, power dissipation and power-delay product (PDP), respectively. Simulation results reveal that the proposed GNRFET-RRAM ternary D-latch offers significantly lower delay, power and PDP making it highly attractive for energy-constrained applications such as embedded systems and IoT devices. This work paves the way for the development of low-power, high-density ternary logic circuits based on emerging nanoscale technologies.