A High-Performance 64-Bit ALU for AI Applications Using Vedic Sutras and Adaptive Accuracy

The Arithmetic Logic Unit, an important part of a processor, performs arithmetic as well as logic computations. The demand for better performance in processors has resulted in improved computational algorithms and multifunctionality, so all processor cores now reside on a single chip, but this again results in high processing burdens. Consequently, coprocessors have been employed in offloading addition, multiplication, and DSP applications to reduce the burden and impact overall speed significantly. This work introduces a 64-bit ALU implemented based on the Vedic Mathematics using Sutras for high-speed calculations. An accuracy-configurable radix-4 adder is used to dynamically control accuracy. Power gating is implemented here in order to optimize performance and power efficiency. The work has been implemented with Verilog HDL and synthesized in Xilinx ISE. The result includes performance improvements over reduced delays.