Design and Performance analysis of Asynchronous Network on Chip for Streaming data Transmission on FPGA

In contemporary Integrated circuit system architectures, on-chip Network has become a standard solution for efficient data packet transfer between nodes, offering low latency, reduced power consumption, and high throughput. Research emphasizes an implementation and validation of asynchronous NoC on FPGAs, utilizing handshake signals inspired by the AXI protocol to optimize performance. The NoC design incorporates network adapters and routers within a mesh topology, facilitating multiprocessor system validation through experimental analysis. Verification and debugging are conducted using the Chip-Scope Pro tool, focusing on modelling asynchronous NoC systems on FPGAs. An advanced NoC with best-effort capabilities is implemented using interconnectors and a label-based switching algorithm for efficient routing. The design includes network interfaces (NIs), UART, and memory for primary handshakes within a four-stage system. A 4×4 NoC with a UART protocol was developed, simulated, and tested using Verilog HDL on an Artix-7 FPGA kit, with Chip-Scope software employed for testing. The routing process utilizes the Label Switching (LS) technique to optimize power consumption, reduce latency, enhance throughput, and conserve bandwidth. The LS-NoC leverages level-encoded dual-rail (LEDR) encoding for streamlined communication, where packets are registered between routers, thereby boosting speed and throughput. Data transfer from source to destination is demonstrated via Virtual Input/Output (VIO) and Integrated Controller (ICON). Performance metrics, including synthesis summary details such as LUTs, slice registers, latency, flip-flops (FFs), and packet delivery ratio (PDR) for the Traffic Pattern Generator, are analysed. The 4×4 NoC design, with a 21-bit port size (MSB for labels and LSB 16 bits for information), achieves a 20% improvement in LUT usage, a 15% reduction in flip-flops, a 30% increase in throughput, and a 26% decrease in delay. The router design was implemented using VIVADO-VHDL software.