A Safe, Secure and Coherent Multi-chip Architecture for ISO Compliant Automotive Solutions

The computational demands of the automotive industry can vary drastically according to the end application. Some applications such as ADAS demand multi-fold performance compared to infotainment systems. With the increasing computational needs, the complexity and the size of modern SoCs are also increasing rapidly. Manufacturing large monolithic chips give lower yield due to likelihood of defects. Design verification and testing of these multiple SoCs of varied performance factors is a costly affair. Chiplets or multi-die systems are an efficient way to address these concerns. Function specific chiplets are designed, verified and are integrated together according to larger computational needs, allowing a flexible, scalable, heterogeneous architecture. This results in higher chips yield during fabrication. Strict safety norms of the automotive industry makes the design of such smaller SoCs challenging, due to the requirements of seamless communication and handshakes, redundancy, coherency, power management and interrupt handling between the multi-chip systems. The host processor in such systems must have a unified view of the memory space, maintain coherency with all the processors in the system, support synchronization and timely handshakes for event management. Interrupt handling must be handled efficiently and in a timely manner and the infrastructure for DFD and DFT must be robust and efficient. In this study, we explore one such system using ARM CPU cluster and GIC architecture for interrupt handling. We outline the challenges faced while designing such systems and possible solutions to counter these issues. Thorough design analysis and preliminary verification attempts prove that such an approach is beneficial to design of complex systems, enabling Original Equipment Manufacturers (OEMs) to transcend the limitations posed by the Moore’s Law.