Multi-State Resistance Tuning via Voltage Ramp Rates in Ni/Mo/MoO3/Ni Memristors for High-Density Memory Applications

Multilevel cell (MLC) storage technology holds significant promise for achieving ultra-high-density memory at a reduced cost. In this study, we demonstrate 2-bit-per-cell storage characteristics in a Ni/Mo/MoO₃/Ni memristor device by tuning input voltage ramp rates (VRR) to obtain different compliance currents (ICC). The Simulation results indicate that the ICC of the device is inversely proportional to VRR, while VSET increases correspondingly. The Ni/Mo/MoO₃/Ni memristor device was designed using the electro-thermal module in the COMSOL Multiphysics tool. The investigation focuses on key MLC operational requirements, particularly switching uniformity and resistance level stability. An engineered stack structure based on thermodynamic principles was developed, comprising a top electrode (Ni), an oxygen vacancy reservoir layer (Mo), a switching layer (MoO3), and a bottom electrode (Ni). By incorporating a 10-nm Mo layer at the Ni/MoOx interface, the optimized device exhibited three distinct low-resistance states while maintaining a single high-resistance state. These states were achieved under different voltage ramp rates— 100 V/s, 10 kV/s, and 1 MV/s—resulting in varying compliance currents (ICC) and VSET values. It is attributed to filament confinement that the switching performance and MLC behavior are improved. According to electrical measurements, this confinement produces favorable electric fields that promote the formation of thin and highly conductive filaments. These findings underscore the potential of the Ni/Mo/MoO₃/Ni memristor for advanced MLC memory applications.