A Half-Bit-Per-Cell Strategy for Enhancing Flash Memory Reliability in Harsh Environments

High bit-density flash memory is widely adopted for cost-effective storage, but its reliability poses significant challenges. An innovative method to enhance reliability and extend the memory lifetime is to reduce the bit-density per cell for wear-out memories. However, exploring further reduction in bit-density beyond the single-bit cell remains an underexplored area of study. In this study, we propose a scheme for achieving half-bit-per-cell (HBPC) storage based on the operation and reliability characteristics of flash memory. We systematically evaluate its effectiveness in enhancing reliability. Our experiments demonstrate a more than 40% increase in cycling endurance with the HBPC scheme. The data retention is also significantly improved from both RBER and sector failure rate perspectives. The proposed scheme will be valuable in applications where SLC is commonly utilized, such as automotive and avionics systems, for further enhancing the reliability and extending the lifespan of the memory.