A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS

The growing demand for higher data throughput accelerates the development of high-speed wireline transceivers with improved energy efficiency and reduced jitter [1]–[3]. A wideband, high-accuracy multi-phase clock generator (MPCG) is a critical component in this development, as it plays a significant role in minimizing jitter on both the transmitter and receiver sides with low-power consumption, as shown in Fig. 1. In recent years, MPCGs have evolved to achieve a wider operating range and lower jitter [4]–[6]. To further extend the operating range, a two-phase injection-locked-ring-oscillator-based (IL-ROSC-based) MPCG with a quadrature-locked loop (QLL) scheme is proposed in [7]. However, the two-phase injection scheme introduces a trade-off between jitter and phase accuracy. To overcome this limitation, a two-step multi-phase injection scheme is proposed in [8]. This approach uses a delay-locked loop (DLL) to generate multi-phase clocks with coarse phase precision for injection, maintaining both low jitter and high phase accuracy. Yet, this method imposes phase accuracy requirements on the clock generated by the DLL, with the DLL's operating range becoming a bottleneck for the operating range of the MPCG. Additionally, the frequency deviation caused by mismatches between the voltage-controlled delay line (VCDL) and the ROSC indicates that the jitter performance of the multiphase clock generator still has potential for further improvement.