Modeling BTI Reliability in CMOS DRAM Periphery Device: A Review of BTI Analysis Tool (BAT)

In this paper we present a review of the BAT framework to model BTI degradation of DRAM CMOS Periphery N and P FETs. DC and AC measurements are performed using ultra-fast measurement methodology. In the first part, the focus is on DC PBTI and NBTI degradation. For both N and P FETs, two gate oxide thicknesses are evaluated and then compared to the model to evaluate the capabilities of the BAT framework. In the second part, the modeling effort is then shifted toward AC BTI degradation. The duty factor and frequency are investigated. Finally, in the last part a discussion on the BAT modeling performances is shared.