ISPI: A 2-Wire Improved Serial Peripheral Interface with Automatic Routing Algorithm for 2-D In-Textile Distributed Computing and Storage Systems

With the rapid improvement of textile integration techniques, smart fabrics are emerging that integrate ultra-small-scale electronics (such as processors, sensors, and memories) into textile surfaces. To maintain the fluidity and comfort of conventional fabrics, smart textiles must use extremely compact components that minimize the number of area-hungry IO pads, which pushes in-textile systems toward disaggregated architectures with numerous tiny components that may span meters across a textile. To demonstrate textile integration, a study directly attaches chips to electrical buses embroidered on textiles [1]. The buses are made with braided composite yarns featuring insulated 25um diameter conductors that have been selectively laser ablated to enable solder attachment. Fig. 1 (top) shows a photo of our 0.6mm x 2.15mm 12-pad chiplet directly connected to the in-textile bus. The severely constrained IO count for such chiplets creates a need for serial, high-bandwidth, and scalable interconnect networks that support variable topologies. However, conventional protocols are designed for integration on printed circuit boards with far fewer components usually on a single shared bus. Fig. 1 (bottom) reviews existing serial protocols that can be used in smart textile systems. Requiring just 2 wires, $\mathrm{I}^{2}\mathrm{C}$ [2] is used in previous e-textile systems [3], [4] but consumes high power due to its pull-up resistor. An $\mathrm{I}^{2}\mathrm{C}$ variant in [5] uses time-divided signal keepers instead of pull-up resistors, but still supports limited data rates. Conventional SPI [6] in a one-dimensional, fiber-like bus reaches higher speeds in [7] but requires an additional chip select (CS) wire for each receiver (RX), which restricts the scalability of pad-limited in-textile systems. Daisy-chain SPI [8] uses only four wires but introduces a latency penalty that scales linearly with the number of RXs. Bypass SPI [9] is a SPI variant aimed at smart textiles that scales by adding layers of linked chiplets, but the limited fanout of 2 downstream devices per chip increases the tree depth and access latency. MBus is a fixed-wire custom ring protocol that achieves low power [10], but its incompatibility with commercial components limits its application in textile systems. To develop a protocol with a low wire count and features for in-textile systems, we propose Improved-SPI (ISPI) as a 2-wire SPI variant that: 1) drops CS and multiplexes MISO/MOSI signals into a shared SDIO wire to allow 2-wire communication, 2) provides multiple combinations of 2 different input and 3 different output configurations to construct flexible 2D networks from layers of ISPI chiplets, 3) simplifies control and lowers overhead with a streamlined 8-bit instruction set, 4) detects and avoids mechanical link failures with an automatic routing algorithm, and 5) can be reconfigured to interface with both commercial off-the-shelf (COTS) and custom RXs.