A High-Speed ASIC Design of Reed–Solomon Erasure Code (RS-EC) Decoders for Fast Data Recovery in Storage

In this letter, a high-speed Reed–Solomon erasure code (RS-EC) decoder circuit is proposed for accelerating the data reconstruction in storage. By utilizing a check matrix instead of a regular Cauchy matrix for encoding the original data, the size of the matrix for decoding the damaged data can be reduced significantly. Moreover, in order to accelerate the matrix inversion related to the RS-EC decoder, the large matrix is partitioned into several small matrices and these small matrices execute the inversion operations individually. Subsequently, an equation method instead of the Gaussian elimination method is proposed for further speeding up the inversions of the small matrices. Eventually, a novel algorithm is proposed for reducing the overall data stream of the RS-EC decoder. The results show that the proposed RS (14, 10) decoder is able to achieve a 6,800 MBps throughput, under the synthesis of TSMC 130 nm process design kits (PDK). The corresponding data stream of the decoder is reduced to 55% if only one data block is required to reconstruct.