Unit-Cell-Based Approach for Electromigration Compliance Checks in VLSI Power Delivery Networks

As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.