Addressing the Connectivity Bottleneck With BEOL FeFETs for 3-D CMOS + X Ising Machines

Recent advancements in Ising machines present an exciting new paradigm for addressing computationally intensive problems with superior energy efficiency and speed compared to conventional digital computers. Despite these promising developments, many real-world problems demand high connectivity, a requirement that exceeds the capabilities of current CMOS-based Ising machine hardware. To overcome this connectivity bottleneck, we propose a novel approach leveraging programmable multibit back-end-of-line (BEOL) ferroelectric field-effect transistor (FeFETs) capable of monolithic 3-D stacking. We experimentally demonstrate a 10-node, 24-coupling Ising machine utilizing dual-gated BEOL FeFETs. This platform enables real-time reconfigurability and supports diverse computational workloads, including combinatorial optimization problems and energy-based learning. Our platform demonstrates robust error-resilient computation with minimal accuracy degradation, even under high endurance conditions of up to 10 billion read and write cycles. This resilience is critical for both read-intensive forward problems and write-intensive inverse or learning problems. To evaluate the performance and area gains, we benchmark the proposed FeFET-based architecture against traditional CMOS implementations. The results reveal significant advantages for FeFET technology, including an $8.2\times $ increase in coupling density, an $11\times $ improvement in energy efficiency, and a $2.1\times $ reduction in latency.