A Novel Layout for Improving Current Sharing of Paralleled SiC MOSFETs with TO-247 Package

Paralleling the silicon carbide (SiC) MOSFETs is necessary to increase the current rating in high-power applications. Moreover, the discrete device with TO-247 package features low-cost, compact, flexible to arrange, and larger cooling area per die. However, it is unclear which layout can offer the best electrical performances such as low loop inductance and parasitic capacitance. Moreover, the current sharing among paralleled devices yields non-negligible issue in device lifetime. This paper covers this gap by comparing performances of different layout options. Furthermore, to address the unbalanced current sharing issue, a novel layout concept is proposed. Both simulations and experimental double-pulse tests (DPT) verify the proposed layout concept. Compared to the conventional laminated layout technique, the proposed layout significantly improves current sharing performance while maintaining a low loop inductance.