A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique

An open-loop fractional output divider (FOD) with self-adaption frequency filtering for digital-to-time converter (DTC) gain and integrated non-linearity (INL) background calibration is presented in this article. The DTC is usually adopted in the FOD to compensate the quantization error. However, the delay of the DTC is sensitive to process, voltage, and temperature (PVT) variations, which necessities gain and INL calibrations. The existing FODs can only perform gain calibration or require prior knowledge to reduce spur level for a certain spur frequency. An FOD with self-adaption frequency filtering is proposed for DTC gain and INL background calibration. Spurious tones generated by the FOD are detected using a PLL-based self-adaption frequency filtering technique. The self-adaption frequency filtering quantifies the deviation of the FOD instantaneous output from its ideal output, which enables a zeroth/first/second-order DTC INL background calibration algorithm for reducing the spur level and jitter. In addition, a discrete-time model of the auxiliary PLL (aux-PLL)-based INL calibration loop is derived and analyzed. Fabricated in the 28-nm CMOS process, the proposed FOD occupies a core area of 0.084 mm² and covers an output range of 10–300 MHz. With a 100-MHz output frequency after the divide-by-2 divider, which corrects the output duty cycle to 50%, the FOD achieves spur level of less than -80 dBc both in the sub-integer-N (int-N) and the fractional-N mode. More than 41.9-dB spur reduction is achieved when enabling the calibration according to measurement results. The FOD achieves a 10-kHz–20-MHz integrated jitter of 310 fs rms.