Enhancing Digital Circuit Efficiency with Memristor-CMOS Hybrid Technology

The demand for electronic memory with higher storage capacity is evolving computers to be smaller, faster, and more reliable. Memristors, newly developed passive components, are gaining attention for their non-volatility and analog behavior. They enhance energy efficiency in digital circuits, particularly when integrated with CMOS technology. This integration optimizes power consumption and improves area and power efficiency. The synergy between memristors and CMOS technology not only creates efficient memory solutions but also boosts computational performance in increasingly compact systems. This paper discusses the integration of a Verilog-A memristor model, which accurately simulates the behaviour of memristive devices using physical equations, into symbol using Cadence Virtuoso. This integration enables the effective use of memristors in Logic Gates and Combinational logics like Half adder, full adder. The memristor-based logic gates, specifically NOT, AND, OR, NOR, NAND gates achieve significant reductions in dynamic power consumption: 88.15%, 87.90%, 79.02%, 77.04%, and 79.47%, respectively, compared to traditional CMOS logic gates using Cadence Virtuoso (45nm Technology) and Power consumed by Memristor based logic gates designed in 45nm,90nm,180nm technologies.