An EDA Based Side-Channel Attack Flamework for Netlists

This paper details a flamework for investigating the resistance of circuits under design to side-channel attacks at the simulation level using general-purpose LSI design tools. Our proposed framework allows logic designers to quickly assess the resistance of designed circuits to power analysis attacks within the context of front-end design, which utilizes hardware description languages such as Verilog HDL or VHDL. The insights gained can be immediately fed back into the logic design process. The framework we have developed will be beneficial to all logic designers concerned with side-channel attack resistance.