Superposition Method of Predicting Junction Temperature of Multi Chip Packages - Important Thermal Parameters

For years, semiconductor industry has observed the trend of increasing number of transistors on a single chip. With the advent of miniaturization transistors' size also tend to shrink and use of different technology nodes on a single package has become advantageous. At the same time the number of transistors on a single chip has increased. Use of multi-chip, including but not limited to computing chips, IO chips, AI chips, memory chips - on a single package has become more useful in terms of performance, functionality etc. Combining all these factors may lead to higher heat flux - thermal management of which can be challenging and may demand innovations in cooling technologies. One key parameter for designing the thermal management solution is the thermal resistance from the heat generating elements to the common casing of the multi-chip package (MCP) or to the surrounding ambient. In a complex MCP each chip may have its own design temperature beyond which the chip might fail or experience lower than expected life - and hence degrade the overall performance of the MCP. Each chip may undergo different power map and power levels - generating its unique junction temperature. To cater for various end users, it is advantageous during the design phase of such MCP to know the junction temperature of all junctions to understand the thermal interaction, limitations and benefits of assigning asymmetric and arbitrary power distribution. To accurately determine the junction temperature with an arbitrary power map, superposition method has been studied and validated in the past with great level of accuracy. In this method the impact of one chip/heat source on other chips/heat sources and on itself is determined and presented as an influence matrix, which is later used to determine the chips' junction temperature when power applied to each chip is known. The influence matrix can be generated from experiments. For MCP with very large number of chips/heat sources it would be more practical to generate this matrix using thermal simulation, while validating a few key cases against experiments. In this study the effects of asymmetry in applied power to the chips and the boundary condition impact on the accuracy of the well-established superposition method has been studied at steady state.