FPGA implementation of Hardware Accelerated 64-bit Floating Point Matrix-Multiplier for GNSS Data Processing

This paper presents FPGA-based implementation of hardware accelerated matrix multiplier using High Level Synthesis (HLS) technique with a specific linkage to GNSS data processing. Matrix multiplication operation is a vital block for GNSS data processing. The multiplication of matrices of order greater than 10 consumes significant time in FPGA-based design. The total time for data processing need to be reduced for real-time scenario specially in case of space-based GNSS applications. For this purpose, HLS IP for matrix multiplication is developed to reduce the processing time substantially. In this work, 64-bit floating point data processing is achieved on 32–bit softcore processor, by design of control logic for seamless dataflow and synchronization between the HLS IP and other key modules in the FPGA. The design is tested in Xilinx Kintex Ultra FPGA-based KCU105 evaluation board. The hardware result for 40x40 matrices show that HLS-based approach achieves speedup factor up to 286 over standalone MicroBlaze softcore processor, this speedup is achieved at the expense of less than 3% percent of available major resources in the FPGA.