Enhancing Edge Performance: A Comparative Analysis of LSTM Inference Using Hardware Acceleration

Field-Programmable Gate Arrays (FPGAs) provide compelling advantages for accelerating Long Short-Term Memory (LSTM) networks, particularly in edge computing applications where performance and power efficiency are critical. This study presents an optimized FPGA-based LSTM accelerator implemented using High-Level Synthesis (HLS) on the PYNQ Z2 board. The proposed design achieves 3.71x performance improvement over a software-based implementation running on the Processing System (PS) of the PYNQ Z2, reducing execution time significantly. The accelerator efficiently utilizes FPGA resources, with 63% LUT and 61% DSP utilization, ensuring a balanced trade-off between computational throughput and hardware constraints. Power analysis reveals that hardware consumes very small fraction of the total power. This study demonstrates that FPGA-based LSTM accelerators provide significant speedup and energy efficiency, making them an attractive solution for real-time, resource-constrained machine learning applications at edge.