Energy Efficient 8T SRAM Cell for Enhancing Read/Write Assist Performances with Stability

The paper proposes a proposed 8T SRAM cell design with a read and write path for read and write operations, which improves read and write stability when compared to the 6T SRAM cells. To solve leakage power concerns, two PMOS transistors were included in the read and write circuitry. This implementation substantially decreases leakage current caused by the induced swing restoration inverter (SRI). The proposed 8T SRAM cells show a significant decrease in leakage current, with reductions of 37.66% and 40.11% compared to 6T SRAM cells. In terms of read latency, the proposed 8T cell surpasses the 6T SRAM cells by 39.80% and 89.13%, respectively. Furthermore, the study reveals a higher speed in write operations, with a 46.97% improvement over the 6T SRAM and a 57.5% gain in performance above the proposed 8T SRAM. The RSNM and WSNM of the suggested 8T SRAM cell were 100 mV and 649 mV, respectively, which shows a considerable improvement compared to the 6T SRAM cell. The performance of the 6T SRAM and suggested 8T SRAM cells is illustrated through simulation studies in the Cadence Virtuoso environment based on the 130 nm technology node.