Design and Optimization of Efficient CNN Hardware of Digital Number Recognition for Low-Power

This paper offers a unique convolutional neural network (CNN) architecture optimized for digital number recognition, emphasising low powerconsumption. The project attempts to create an efficientCNN-based system capable of detecting digital numbers in power-constrained conditions. We use a cutting-edge YOLO-NAS model and FPGA (Field Programmable Gate Array) technology to improve processing efficiency and minimize energy consumption. The technique consists of many critical components. First, we train the YOLO-NAS model using a large dataset from Roboflow, which includes extensive annotations for digital number recognition. The model is then modified for FPGA implementation, necessitating changes to accommodate FPGA-specific limitations and assure compatibility. To enhance the model performance, we use quantization techniques and pruning strategies, particularly the L1 norm-based pruning strategy, which reduces model size and Computing demand while maintaining accuracy. Thefindings reveal that our FPGA-based YOLO-NAS modeloutperforms traditional GPU-based systems in terms of power efficiency while not influencingrecognition performance. The model performs well in real-time digital number recognition tests, showing its usefulness in low-power applications. This study overcomes the issues of power consumption and processing efficiency, providing a scalable approach appropriate for edge computing applications. By combining YOLO-NAS with FPGA, the research opens the path for more sustainable and efficient digital recognition systems.