Low-Power MIPS32 Processor Design with Cache Implementation Using Clock Gating Techniques on FPGAs

This paper presents the design and implementation of a low-power MIPS32 processor with an integrated cache system, leveraging clock gating techniques to optimize power efficiency on Field-Programmable Gate Arrays (FPGAs). Clock gating is employed to reduce dynamic power consumption by selectively disabling the clock signal in inactive functional units, thereby minimizing unnecessary switching activity. The proposed architecture incorporates an optimized cache memory hierarchy to enhance performance while maintaining energy efficiency. Experimental results demonstrate significant reductions in power consumption without compromising processing speed., making this design well-suited for power-constrained applications such as embedded systems and IoT devices.