Preliminary Design of Camera Data Receiver System for High Data Rate on LAPAN-A4 Satellite Using FPGA and LVDS

The primary mission of the LAPAN-A4 satellite is earth observation using the Medium Resolution Imager (MRI) camera. The main challenge in this system is transmitting large-scale data in real-time from the MRI to the Payload Data Handling System with stable clock synchronization. To achieve this challenge, Field Programmable Gate Array (FPGA) technology was chosen for its flexibility in reprogramming and parallel processing capability. Meanwhile, Low Voltage Differential Signaling (LVDS) was chosen for its ability to transmit data at high speed and reduce noise. This research designs an FPGA and LVDS-based data receiver system with a data rate of up to 178.276 Mbps. VHDL-based simulations were performed to identify potential issues and verify system performance. The system was evaluated through simulations to measure its bandwidth and frame repetition time, demonstrating that it achieved a bandwidth of 178.276 Mbps with a frame repetition time of 2.27171 ms. Additionally, performance evaluation through the simulation confirmed the system’s capability to process large volumes of data at high speed. Although the simulation results are close to the expected specifications, further optimization related to clock synchronization and data processing is still needed to achieve optimal performance in hardware implementation.