Low-Power Approximate Computing-based VLSI Architecture for Biomedical Signal Processing

The analysis of ECG, EEG and EMG signals requires biomedical signal processing which needs low-power high-performance VLSI architectures to achieve real-time processing. This paper introduces an optimized VLSI architecture which enables biomedical signal processing through energy-efficient digital filtering along with feature extraction as well as pipeline-based clock gating. The proposed architecture combines a distributed arithmetic FIR filter without multipliers to reduce complexity and it integrates a low-power feature extraction system that detects ECG R-peaks and EEG spectral energy and EMG muscle activity effectively. The system uses dynamic clock gating together with power gating to cut down both dynamic power usage and leakage power. The experimental findings show that the developed VLSI architecture both reduces power usage through low hardware complexity while keeping high accuracy levels for biomedical signal processing. The system delivers its performance measurement through power dissipation and area efficiency along with processing speed which enables its use in wearable and implantable medical devices.