SIMMAC: SRAM IMC-Based Multi-bit Multiplication With Analog Carry Computation

Several applications, ranging from artificial intelligence to encryption, require dense multi-bit matrix multiplications. With the advent of big-data applications and edge deployment, a recent paradigm shift focuses on energy-efficient computation methodologies such as In-Memory Computing (IMC). In this work, we propose SRAM IMC based Multi-bit Multiplication with Analog Carry computation (SIMMAC), a novel 8T SRAM-based IMC accelerator for multi-bit multiplication with reconfigurable bit-precision. To address the present-day challenges of IMC architectures, we propose a novel input and weight mapping strategy along with analog carry addition for in-memory computation. The proposed input and weight mapping strategy renders the implementation to be DAC-less, hence boosting the performance of the IMC Macro in terms of area and power. The novel analog carry addition methodology computes the multi-bit product within the IMC Macro, eliminating the need for peripheral digital shift-and-add circuits. With the proposed Convolutional Neural Network(CNN) workload mapping analyzed in this study, our architecture executes the Matrix Vector Multiplication (MVM) across all tiles in a single product cycle of 40ns. Our architecture achieves 98% accuracy for MNIST classification and 819.2 GOPS and 56.5 TOPS/W at 200MHz operating frequency at TSMC 65 nm technology node.