Efficient Multiplier design using CNTFET

Binary multiplier has been playing a vital role in digital signal processing, Arithmetic logic Unit (ALU), Embedded systems and Machine Learning. The multiplier has been designed using CMOS for a long time. Carbon Nanotube Field-Effect Transistors (CNTFETs), by virtue of their remarkable electrical capabilities, offer a promising solution for the electronics of the future. Their importance is further highlighted by their ability to counteract short-channel effects in conventional CMOS technology, which are linked to greater carrier mobility and improved electrostatic control. In this work, a two-bit multiplier is constructed utilizing a variety of CMOS technologies. The carbon nanotube field effect transistor (CNTFET) is utilized to get around the CMOS multipliers' power and delay constraints. Using the Cadence Virtuoso tool, a comparison of several CMOS multipliers that are now in use and those that have been proposed is conducted. Predictive Technology Models (PTM) are utilized for CMOS, while Stanford CNFET Model – Verilog-A is used for CNTFET analysis.