Towards Polynomial Formal Verification of Neuromorphic Architectures

With the growing use of Artificial Intelligence various Neural Processing Units (NPUs) are becoming increasingly popular. At the core of these processors are the Multiply and Accumulate (MAC) operations. As processors with complex functionalities become more relevant in the AI era, it is imperative to have efficient verification strategies to circumvent costly errors. In this context Polynomial Formal Verification (PFV) has recently been introduced. As compared to classical formal verification, PFV ensures not only 100% correctness, but also provides an estimate of time and space within polynomial bounds. PFV has successfully been applied for various formal proof engines, like Binary Decision Diagrams (BDD), Satisfiability (SAT), Answer Set Programming (ASP), Symbolic Computer Algebra (SCA). BDDs, SAT and ASP have been used to efficiently verify adders whereas SCA was applied to multipliers. The question arises how to exploit the benefits of these polynomially verified sub-components in solving more complex designs. In this paper we investigate how this can be applied to NPUs, particularly we show experimental studies for MAC operations. It is shown that verifiability of the MAC operation heavily depends on the realization of the underlying circuit.