Low-latency, high-speed numerically controlled oscillator using progression-of-states technique

A progression-of-states design technique for numerically controlled oscillators (NCOs) has measured a decrease in 16-bit accumulator latency to two clock cycles for a 130-MHz device in a 1.0- mu m CMOS gate array. An enhanced version derived and simulated directly from fabricated device has been projected to accumulate at 267 MHz.<>