Built-in testable error detection and correction

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1- mu m CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 mu s at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test.<
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