A 470-μW, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC

This article presents the first true multi-bit discrete-time ΔΣ modulator (DTΔΣ M) to achieve a spurious-free dynamic range (SFDR) in excess of 110 dBc without the need for dynamic element-matching (DEM) or calibration. This high linearity is obtained by employing a 13-level intrinsically linear digital-to-analog converter (DAC) where capacitor and reference voltage mismatches are only second-order sources of non-linearity. The linearity performance is validated across multiple samples and over supply voltage and temperature variation. The prototype achieves a dynamic range (DR) of 102.6 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.7 dB in a 20-kHz bandwidth (BW), consuming 470 μW from a 1.8 V supply including on-chip reference generation and buffers, and resulting in a Schreier figure-of-merit (FoM) of 178.9 dB.