Performance Analysis of MAC Unit with Various Parallel Adders

The Multiply-Accumulate (MAC) Unit is a crucial component in all DSP Applications, due to its ability to perform high-speed arithmetic operations. This research aims to design and implement an 8-bit MAC Unit capable of performing multiplication and accumulation operations. The MAC Unit employs the same multiplier but integrates different adders such as Kogge-Stone, Ladner-Fischer, Carry Look-Ahead adder, and Ripple Carry Adder. The structures were formed using Verilog Hardware Description Language (HDL) and implemented on Xilinx ISE, with simulation carried out using ModelSim.