Implementation of Baugh-Wooley Multiplier Using Hybrid Full Adder

The majority of the most recent data-driven advancements, notably artificial-intelligence (AI) and machine-learning (ML) depend heavily on binary arithmetic computations. This paper focuses on the design and analysis of a reliable, low-power 4-bit Baugh- Wooley (BW) multiplier employing the high-performance Hybrid full adder using XOR-XNOR cell. The effectiveness of the proposed 4-bit BW multiplier is thoroughly investigated for power and delay parameters at different operating voltages. The proposed 4-bit BW multiplier at a CMOS process employing a hybrid full adder circuit consumes a minimal power of 303.1 nW at an operating voltage of 1 V. The power consumption increases linearly with operating voltage for the designed BW multiplier employing the high performance full- adder circuits. The proposed 4-bit BW multiplier has a delay of 3.91 ps at 1 V. The simulation result analysis indicates the combination of XOR-XNOR cell in the design of low-power 4-bit Baugh-Wooley multipliers.