Comparative Analysis of Performance Factors of an 8-bit SIPO Shift Register using JK Flip-Flop with a Very Low Dynamic Power and High Noise Margin

This paper undertakes a comprehensive comparative analysis of Serial-In-Parallel-Out (SIPO) shift register circuit design constructed using Master-Slave JK flip-flops employing five distinct technologies, e.g., Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), Transmission Gate (TG), Pass Transistor (PT), and Pseudo-NMOS Logic circuit. Each technology’s design process and key performance parameters of an 8-bit SIPO shift register are thoroughly investigated and compared, focusing on critical performance metrics of the SIPO shift register. The study extends its analysis by contrasting the performance parameters of the JK flip-flops, which is the main constituent of the 8 -bit SIPO shift register, designed with these technologies against previous research findings. Our analysis shows a very low dynamic power consumption of $14.1 ~\mu \mathrm{W}$, area of $839.14 \mathrm{~nm}^{2}$, propagation delay of 5.6 ns, slew rate of $79.75 \mathrm{GV} / \mathrm{s}$, and a high noise margin of $\mathrm{5 0. 1 8 ~ \mathrm { ~ m V }}$. This study stands out as a significant progression in performance metrics. Results demonstrate the competitive advantages and trade-offs inherent in each technology with new findings for the SIPO shift register. This offers valuable guidance for digital circuit designers in selecting the most suitable approach for digital circuit implementations.