Asynchronous SRAM: Towards Energy-Efficient Solutions

This paper focuses on design and implementation of an asynchronous SRAM system utilizing memory banking techniques on a 45 nm technology. This system comprises four 16KB SRAM and a 2 -to- $\mathbf{4}$ decoder, collectively forming a 64 KB memory space. The asynchronous nature of SRAM allows for independent read and write operations, enhancing speed and efficiency crucial for various applications. The 2-to-4 decoder facilitates memory bank selection based on address lines, enabling seamless access to desired memory locations. Chip select, output enable, and write enable signals control memory operations, ensuring data integrity and efficient power usage. Power distribution analysis reveals that the leakage power with the effectiveness of memory banking(64 KB) in reducing power consumption compared to the single-block design (16KB). The simulation results and power distribution analysis, the study demonstrates the effectiveness of memory banking techniques in reducing leakage power.