A Compact and Low-Loss D-Band SPDT Switch Using 65-nm CMOS Technology

A compact CMOS single-pole double-throw (SPDT) switch employing a parallel configuration of shunt transistors is proposed to achieve low insertion loss in the D-band. The parallel configuration of switching transistors, which reduces the on-resistance of the active transistor, inherently enhances the off-state isolation in the proposed SPDT switch employing shunt transistors. Additionally, the increased off-capacitance of the inactive shunt transistors in this configuration reduces insertion loss by effectively shortening the transmission line through increased capacitive loading. The proposed SPDT switch was fabricated using a 65-nm bulk CMOS process, achieving a compact core chip area of 0.03 mm2. Measurement results demonstrate an on-state insertion loss of 1.7 dB and an off-state isolation of 18 dB at an operating frequency in the D-band. The simulated input $P_{\text {1 dB}}$ at 150 GHz is 15 dBm.