A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces

This paper introduces a three-level pulse amplitude modulation single-ended transmitter using V_M (half of $\text{V}_{\mathrm {DDQ}}$ ) termination, designed for next-generation low-power memory interfaces. The proposed signaling strategy, based on the V_M termination, improves signal integrity by reducing signaling current by 41.05% while maintaining the same voltage swing compared to existing V_SS-terminated structures for low-power memory interfaces. This reduction in signaling current effectively decreases simultaneous switching output noise. Additionally, this approach alleviates the voltage headroom limitation and enables pre-emphasis adoption, resulting in a larger voltage swing and reduced power consumption compared to de-emphasis. The voltage difference between the drain and source of each pull-up and pull-down driver is balanced, achieving a good ratio of level mismatch (RLM). Moreover, the three-step ZQ calibration and transmission gate-based receiver-side V_M termination help achieve accurate on-resistance and improve output linearity, reducing signal reflection. The prototype chip, fabricated using a 65-nm CMOS process, has an area of 0.0184 mm². It achieves a data rate of 22.5 Gb/s with an energy efficiency of 0.86 pJ/bit and a measured RLM of 99.2%.