Area and Power Efficient Modified Karatsuba Multiplier for Error-Free Cryptography Algorithms

Data security and authentication are critical in cryptography, especially in elliptic curve cryptography (ECC), where usage of efficient finite field multipliers becomes essential. However, these multipliers consume significant hardware resources and impact performance. This paper investigates the Karatsuba algorithm and its variants to improve hardware efficiency on FPGA devices. While the overlap-free Karatsuba algorithm enhances performance. They introduce 20% errors due to issues in recombining intermediate results. To address this, a modified Karatsuba algorithm is proposed for error-free computation of four key outputs for 2-bit inputs. Implemented in Verilog HDL and evaluated on Artix-7 FPGA, the modified design reduces area usage by 95% and power consumption by 73.95% compared to the original Karatsuba algorithm. Although it shows a 3.22% increase in area and 11.12% in power compared to the overlap-free version, it significantly improves overall efficiency while ensuring accuracy.