Time-Domain Argmax Architecture for the Tsetlin Machine Classification

Machine Learning (ML) techniques have expanded the boundaries of artificial intelligence, especially in pattern recognition, automated decision-making, and data analysis. Nonetheless, the hardware implementation of maxima arguments (argmax), significant in ML algorithms, has increasingly become a limiting factor in edge computing. As the dataset grows, traditional argmax methods, including magnitude or Hamming comparators, face challenges related to excessive resource demands, slower response times, and higher power consumption. The Tsetlin machine (TM), as an emerging propositional logic-based ML algorithm, has interpretability and hardware affinity. This paper proposes a time-domain argmax architecture well-suited for the TM inference process. The architecture converts the arithmetic operations of input variables into delay accumulation. It grants the maximal variable by arbitrating the first-arrive signal based on the winner-takes-all principle. The design flow is based on a four-phase “handshake” logic for quasi-delay insensitivity, where the signal transitions' causality is modeled by a signal transition graph. The proposed design has been successfully validated on Cadence platforms utilizing TSM C 65nm technology, demonstrating a considerable size reduction compared to conventional HDL-based argmax circuits. Moreover, as the input data set expands, the design's energy efficiency significantly improves.