9T SRAM Cell Based Wired-OR Logic Arrays for Tsetlin Machine Inference

Tsetlin Machine (TM) has recently emerged as a promising alternative to arithmetically driven machine learning algorithms, such as deep neural networks (DNNs). TMs are based on single-layered propositional logic followed by summative voting between conjunctive clauses. Although, the logic underpinning has been demonstrated with significantly lower complexity than DNNs, TM's memory footprint can grow dramatically when the model size increases. While designing hardware accelerator architecture, such an increase in the complexity can be associated with significantly increased data movement overheads. In this paper, we propose a processing in-memory (PIM) inspired TM inference architecture. Central to this architecture are 9-transistor (9T) static random access memory (SRAM) Wired-OR logic arrays, fitting the natural logic underpinning of TM. The implementation of Wired-OR logic using 9T SRAM cells provides the crucial embedding of logic with storage, thereby reducing the overall logic complexity and data movement costs significantly. Through extensive simulations, we analyze the functional properties of the inference accelerator. Further, we study scalability under multiple Tsetlin automata scenarios and investigate parametric behaviors such as power consumption, PVT variations and Monte Carlo simulations. We show that our design achieves 72 % area reduction per TA propositional logic when compared with a vanilla CMOS design implementing the TAs using flip-flops.