A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop

Wide-band wireless system-on-chip demands phase-locked loops(PLL) designed with multi-band voltage controlled oscillators (VCO), which requires auto frequency calibration (AFC) for frequency presetting. This paper proposes a high-speed energy-efficient integrated AFC with asynchronous hybrid searching technique. The asynchronous architecture breaks the minimum limit of search time, while the hybrid method overcomes nonmonotonic variation of frequency errors in binary search. A true single-phase clock (TSPC)-based RF digital counter further accelerates AFC by directly quantizing the VCO output frequency. In this paper, a 3.2 GHz PLL is presented utilizing the high-speed AFC to achieve fast locking performance. Implemented in 28nm CMOS technology, the proposed AFC for a 7-bit VCO achieves a calibration time of 0.88-4.74$\boldsymbol{\mu}$s across available tuning range, while the time of each step reaches 120ns level. With the aid of AFC, the prototype PLL reaches settle in less than 11.8$\boldsymbol{\mu}$s, while achieving 318.2 fs integrated jitter and -64.3 dBc reference spur. The Figure-of-Merit (FoM) of the 3.2 GHz PLL achieves -239.66 dB for FoM_jitter, and -186.16 dB for FoM_TS.