Performance optimization techniques of dynamic latched comparator

A systematic study on various double tail comparator architectures is done to analyze the various topological changes in both stages, clocking strategies, cross connected loads, Induced delays to hold the gain, and many other structural as well as logical alternatives. This paper gives an overview of highly preferred strategies to reduce power consumption and delay of the comparator. Further these strategies can be implemented along with other topological changes to compromise conventional trade off like power consumption – offset, Kickback noise-delay and so on.