A Comprehensive Literature Review on Core Local Interrupt Controller in RISC-V Processors

The emergence of an open-source instruction set architecture (ISA) widely known as RISC-V has opened a new era of innovation within the realm of embedded systems. Interrupt handling is a crucial aspect in RISC-V-based processors enabling the timely response to external events and ensuring efficient task management. However, it is important to acknowledge that there are still certain gaps between the current interrupt capabilities of RISC-V and the evolving requirements of emerging computing scenarios. The Core Local Interrupt Controller (CLIC) has emerged as a crucial enhancement in RISC-V processors addressing the limitations of the Core Local Interruptor (CLINT), the default interrupt controller, in interrupt prioritization and pre-emption. This paper provides a comprehensive review of the CLIC, delving into its functionalities, key components, and methodologies, leveraging various research papers and publications. Drawing insights from various research papers, journals, articles, and publications, the comprehensive analysis herein sheds light on the critical role played by the CLIC in overcoming challenges related to interrupt prioritization and pre-emption in RISC-V-based processors. Furthermore, this paper concludes by identifying open research challenges and emerging trends in the field of CLIC implementation and utilization.